STMicro STM8S103F3P6 MCU Chip Breaking refers to flash memory of CPU STM8S103F3P6 tamper resistance system unlocking and then readout embedded heximal from microcontroller stm8s103f3 flash memory;
SPI
Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave
Full duplex synchronous transfers
Simplex synchronous transfers on two lines with a possible bidirectional data line
Master or slave operation – selectable by hardware or software
CRC calculation
1 byte Tx and Rx buffer
Slave/master selection input pin
I2C
I2C master featuresClock generationStart and stop generationI2C slave featuresProgrammable I2C address detectionStop bit detectionGeneration and detection of 7-bit/10-bit addressing and general callSupports different communication speedsStandard speed (up to 100 kHz)Fast speed when breaking micro stm8s103f3 flash memory (up to 400 kHz).
As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits.
Refer to Section 8: Option bytes. When the remapping option is active, the default alternate function is no longer available in the process of breaking stm8s103k3 microcontroller protection.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0016).