Break IC, Recover MCU, Microcontroller Reverse Engineering

Attack Chip PIC18F66K90 starts from decapsulate the microcontroller silicon package and locate the security fuse bit which has been viewed an most commonly way to crack MCU, then extract the software out from the memory;

Low-Power Features:

· Power-Managed modes:

– Run: CPU on, peripherals on

– Idle: CPU off, peripherals on

– Sleep: CPU off, peripherals off

· Two-Speed Oscillator Start-up

· Fail-Safe Clock Monitor

· Power-Saving Peripheral Module Disable (PMD)

· Ultra Low-Power Wake-up

· Fast Wake-up, 2 ms Typical

· Low-Power WDT, 300 nA Typical

· Ultra Low 50 nA Input Leakage

· Run mode Currents Down to very low 5.5 mA, Typical

· Idle mode Currents Down to very low 2.2 mA, Typical

· Sleep mode Current Down to very low 20 nA, Typical

· RTCC Current Down to very low 700 nA, Typical

· LCD Current Down to very low 300 nA, Typical

LCD Driver and Keypad Features:

· Direct LCD Panel Drive Capability:

– Can drive LCD panel while in Sleep mode

· Up to 48 Segments and 192 Pixels, Software-Selectable

· Programmable LCD Timing module:

– Multiple LCD timing sources available

– Up to four commons: static, 1/2, 1/3 or 1/4 multiplex

– Bias configuration: Static, 1/2 or 1/3

· Low-Power Resistor Bias Network for LCD

Peripheral Highlights:

· Ten or eight CCP/ECCP modules:

– Seven Capture/Compare/PWM (CCP) modules

– Three Enhanced Capture/Compare/PWM (ECCP) modules

· Eleven 8/16-Bit Timer/Counter modules:

– Timer0 – 8/16-bit timer/counter with 8-bit programmable prescaler

– Timer1,3,5,7 – 16-bit timer/counter

– Timer2,4,6,8,10,12 – 8-bit timer/counter

· Three Analog Comparators

· Configurable Reference Clock Output

· Hardware Real-Time Clock and Calendar (RTCC) module with Clock, Calendar and Alarm Functions

– Time-out from 0.5s to 1 year

· Charge Time Measurement Unit (CTMU)

– Capacitance measurement for mTouch™ Sensing

– Time measurement with 1 ns typical resolution

· High-Current Sink/Source 25 mA/25 mA (PORTB and PORTC)

· Up to Four External Interrupts

· Two Master Synchronous Serial Port (MSSP) modules:

– 3/4-wire SPI (supports all four SPI modes)

– I2C™ Master and Slave mode

Special Microcontroller Features:

· Priority Levels for Interrupts

Operating Voltage Range: 1.8V to 5.5V

On-Chip 3.3V Regulator

Operating Speed up to 64 MHz

Up to 128 Kbytes On-Chip Flash Program Memory Data EEPROM of 1,024 Bytes

4K x 8 General Purpose Registers (SRAM)

10,000 Erase/Write Cycle Flash Program

Memory, Typical 1,000,000 Erase/write Cycle Data EEPROM

Memory, Typical Flash Retention 40 Years, Minimum

Three Internal Oscillators: LF-INTRC (31 kHz),

MF-INTOSC (500 kHz) and HF-INTOSC (16 MHz)

Self-Programmable under Software Control

· 8 x 8 Single-Cycle Hardware Multiplier

· Extended Watchdog Timer (WDT):

– Programmable period from 4 ms to 4,194s (about 70 minutes)

· In-Circuit Serial Programming™ (ICSP™) via

Two Pins

· In-Circuit Debug via Two Pins

· Programmable:

– BOR

– LVD

· Two Enhanced Addressable USART modules:

– LIN/J2602 support

– Auto-Baud Detect (ABD)

· 12-Bit A/D Converter with up to 24 Channels:

– Auto-acquisition and Sleep operation

– Differential Input mode of operation

Attack Microcontroller PIC18F66K90 locked memory cell include flash and eeprom, disable the security fuse bits and get access to the databus of MCU then readout the Heximal and clone content to new IC;

Low-Power Features:

· Power-Managed modes:

– Run: CPU on, peripherals on

– Idle: CPU off, peripherals on

– Sleep: CPU off, peripherals off

· Two-Speed Oscillator Start-up

· Fail-Safe Clock Monitor

· Power-Saving Peripheral Module Disable (PMD)

· Ultra Low-Power Wake-up

· Fast Wake-up, 2 ms Typical

· Low-Power WDT, 300 nA Typical

· Ultra Low 50 nA Input Leakage

· Run mode Currents Down to very low 5.5 mA, Typical

· Idle mode Currents Down to very low 2.2 mA, Typical

· Sleep mode Current Down to very low 20 nA, Typical

· RTCC Current Down to very low 700 nA, Typical

· LCD Current Down to very low 300 nA, Typical LCD Driver and Keypad Features:

· Direct LCD Panel Drive Capability:

– Can drive LCD panel while in Sleep mode

· Up to 48 Segments and 192 Pixels, Software-Selectable

· Programmable LCD Timing module:

– Multiple LCD timing sources available

– Up to four commons: static, 1/2, 1/3 or 1/4 multiplex

– Bias configuration: Static, 1/2 or 1/3

· Low-Power Resistor Bias Network for LCD Peripheral Highlights:

· Ten or eight CCP/ECCP modules:

– Seven Capture/Compare/PWM (CCP) modules

– Three Enhanced Capture/Compare/PWM (ECCP) modules

· Eleven 8/16-Bit Timer/Counter modules:

– Timer0 – 8/16-bit timer/counter with 8-bit programmable prescaler

– Timer1,3,5,7 – 16-bit timer/counter

– Timer2,4,6,8,10,12 – 8-bit timer/counter

· Three Analog Comparators

· Configurable Reference Clock Output

· Hardware Real-Time Clock and Calendar (RTCC) module with Clock, Calendar and Alarm Functions

– Time-out from 0.5s to 1 year

· Charge Time Measurement Unit (CTMU):

– Capacitance measurement for mTouch™ Sensing

– Time measurement with 1 ns typical resolution

· High-Current Sink/Source 25 mA/25 mA (PORTB and PORTC)

· Up to Four External Interrupts

· Two Master Synchronous Serial Port (MSSP) modules:

– 3/4-wire SPI (supports all four SPI modes)

– I2C™ Master and Slave mode

Special Microcontroller Features:

· Priority Levels for Interrupts

Operating Voltage Range: 1.8V to 5.5V

On-Chip 3.3V Regulator

Operating Speed up to 64 MHz

Up to 128 Kbytes On-Chip Flash Program Memory Data EEPROM of 1,024 Bytes

4K x 8 General Purpose Registers (SRAM)

10,000 Erase/Write Cycle Flash Program

Memory, Typical 1,000,000 Erase/write Cycle Data EEPROM

Memory, Typical Flash Retention 40 Years, Minimum

Three Internal Oscillators: LF-INTRC (31 kHz),

MF-INTOSC (500 kHz) and HF-INTOSC (16 MHz)

Self-Programmable under Software Control

· 8 x 8 Single-Cycle Hardware Multiplier

· Extended Watchdog Timer (WDT):

– Programmable period from 4 ms to 4,194s (about 70 minutes)

· In-Circuit Serial Programming™ (ICSP™) via Two Pins

· In-Circuit Debug via Two Pins

· Programmable:

– BOR

– LVD

· Two Enhanced Addressable USART modules:

– LIN/J2602 support

– Auto-Baud Detect (ABD)

· 12-Bit A/D Converter with up to 24 Channels:

– Auto-acquisition and Sleep operation

– Differential Input mode of operation

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Module: Analog-To-Digital Converter (ADC) Module

Selecting the VP6 reference as the analog input source (CHS<3:0> = 1111) for the ADC conversion after sampling another analog channel with input voltages approximately greater than 3.6V can temporarily disturb the HFINTOSC oscillator.

4. Module: MSSP (SPI Master Mode)

With MSSP in SPI Master mode, FOSC/64 or Timer2/2 clock rate and CKE = 0, a write collision may occur if SSPBUF is loaded immediately after the transfer is complete after Attack MCU. A delay may be required after the MSSP Interrupt Flag bit, SSPIF, is set or the Buffer Full bit, BF, is set and before writing SSPBUF. If the delay is insufficiently short, a write register and NOT during the start of an actual ADC conversion using the GO/DONE bit in the ADCON0 register.

This only occurs when selecting the VP6 reference ADC channel using the CHS<3:0> bits in the ADCON0 collision may occur as indicated by the WCOL bit being set.

 

Select an ADC channel with input voltages lower than 3.6V prior to selecting the VP6 reference voltage input. Any analog channel can be used, even if that channel is configured as a digital I/O (configured as an output) that is driving the output pin low when Attack MCU. An alternative is to configure the CVREF module to output a voltage less than 3.6V and then selecting that analog channel CHS<3:0> = 1110 as the analog input source.

Add a software delay of one SCK period after detecting the completed transfer and prior to updating the SSPBUF contents. Verify the WCOL bit is clear after writing SSPBUF. If the WCOL is set, clear the bit in software and rewrite the SSPBUF register.

Date Codes that pertain to this issue:

All engineering and production devices.

Affected Silicon Revisions

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Power Management Features:

Peripheral Highlights (Continued):

Run: CPU on, Peripherals on

Idle: CPU off, Peripherals on

Sleep: CPU off, Peripherals off

Ultra Low 50nA Input Leakage

Run mode Currents Down to 11 ìA Typical

Idle mode Currents Down to 2.5 ìA Typical

Sleep mode Current Down to 100 nA Typical

Timer1 Oscillator: 900 nA, 32 kHz, 2V

Watchdog Timer: 1.4 ìA, 2V Typical

Two-Speed Oscillator Start-up

 

· Master Synchronous Serial Port (MSSP) module

Supporting 3-Wire SPI (all 4 modes) and I2C™ Master and Slave modes

· Enhanced Addressable USART module:

– Supports RS-485, RS-232 and LIN/J2602

– RS-232 operation using internal oscillator

block (no external crystal required)

– Auto-wake-up on Start bit

– Auto-Baud Detect

· 10-Bit, up to 13-Channel Analog-to-Digital (A/D)

 

Flexible Oscillator Structure:

· Four Crystal modes, up to 40 MHz

· 4x Phase Lock Loop (PLL) – Available for Crystal and Internal Oscillators

· Two External RC modes, up to 4 MHz

· Two External Clock modes, up to 40 MHz

· Internal Oscillator Block:

– Fast wake from Sleep and Idle, 1 ìs typical

– 8 use-selectable frequencies, from 31 kHz to 8 MHz

– Provides a complete range of clock speeds from 31 kHz to 32 MHz when used with PLL

– User-tunable to compensate for frequency drift

· Secondary Oscillator using Timer1 @ 32 kHz

· Fail-Safe Clock Monitor:

– Allows for safe shutdown if peripheral clock stops

 

Peripheral Highlights:

 

Converter module:

– Auto-acquisition capability

– Conversion available during Sleep

· Dual Analog Comparators with Input Multiplexing

· Programmable 16-Level High/Low-Voltage Detection (HLVD) module:

– Supports interrupt on High/Low-Voltage Detection

Special Microcontroller Features:

· C Compiler Optimized Architecture:

– Optional extended instruction set designed to optimize re-entrant code

· 100,000 Erase/Write Cycle Enhanced Flash

Program Memory Typical

· 1,000,000 Erase/Write Cycle Data EEPROM

Memory Typical

· Flash/Data EEPROM Retention: 100 Years Typical

· Self-Programmable under Software Control

High-Current Sink/Source 25 mA/25 mA

Three Programmable External Interrupts

Four Input Change Interrupts

Up to 2 Capture/Compare/PWM (CCP) modules,

 

· Priority Levels for Interrupts

· 8 x 8 Single-Cycle Hardware Multiplier

· Extended Watchdog Timer (WDT):

– Programmable period from 4 ms to 131s one with Auto-Shutdown (28-pin devices)

· Enhanced Capture/Compare/PWM (ECCP) module (40/44-pin devices only):

– One, two or four PWM outputs

– Selectable polarity

– Programmable dead time

– Auto-shutdown and auto-restart

· Single-Supply 5V In-Circuit Serial

Programming™ (ICSP™) via Two Pins

· In-Circuit Debug (ICD) via Two Pins

· Wide Operating Voltage Range: 2.0V to 5.5V

· Programmable Brown-out Reset (BOR) with Software Enable Option

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16-Bit Single-Chip Microcontroller C164CI/SI, C164CL/SL

· High Performance 16-bit CPU with 4-Stage Pipeline

– 80 ns Instruction Cycle Time at 25 MHz CPU Clock

– 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)

– Enhanced Boolean Bit Manipulation Facilities

– Additional Instructions to Support HLL and Operating Systems

– Register-Based Design with Multiple Variable Register Banks

– Single-Cycle Context Switching Support

– 16 MBytes Total Linear Address Space for Code and Data

– 1024 Bytes On-Chip Special Function Register Area

· 16-Priority-Level Interrupt System with 32 Sources, Sample-Rate down to 40 ns

· 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via

Peripheral Event Controller (PEC)

· Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5) via prescaler or via direct clock input

· On-Chip Memory Modules

– 2 KBytes On-Chip Internal RAM (IRAM)

– 2 KBytes On-Chip Extension RAM (XRAM)

– up to 64 KBytes On-Chip Program Mask ROM or OTP Memory

· On-Chip Peripheral Modules

– 8-Channel 10-bit A/D Converter with Programmable Conversion Time down to 7.8 µs

– 8-Channel General Purpose Capture/Compare Unit (CAPCOM2)

– Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6) (3/6 Capture/Compare Channels and 1 Compare Channel)

– Multi-Functional General Purpose Timer Unit with 3 Timers

– Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)

– On-Chip CAN Interface (Rev. 2.0B active) with 15 Message Objects (Full CAN/Basic CAN)

– On-Chip Real Time Clock

· Up to 4 MBytes External Address Space for Code and Data

– Programmable External Bus Characteristics for Different Address Ranges

– Multiplexed or Demultiplexed External Address/Data

– Four Optional Programmable Chip-Select Signals

· Idle, Sleep, and Power Down Modes with Flexible Power Management

· Programmable Watchdog Timer and Oscillator Watchdog

· Up to 59 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis

· Supported by a Large Range of Development Tools like C-Compilers,

Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,

Simulators, Logic Analyzer Disassemblers, Programming Boards

· On-Chip Bootstrap Loader

· 80-Pin MQFP Package, 0.65 mm pitch

This document describes several derivatives of the C164 group. Table 1 enumerates these derivatives and summarizes the differences. As this document refers to all of these derivatives, some descriptions may not apply to a specific product.

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High-Performance RISC CPU:

· Only 35 Instructions to Learn

– All single-cycle instructions except branches

· Operating Speed:

– DC – 20 MHz oscillator/clock input when Break Microcontroller

– DC – 200 ns instruction cycle

· Interrupt Capability

· 8-Level Deep Hardware Stack

· Direct, Indirect, and Relative Addressing modes

Special Microcontroller Features:

· Internal and External Oscillator Options

– Precision Internal 4 MHz oscillator factory calibrated to ±1%

– External Oscillator support for crystals and resonators

– 5 ms wake-up from Sleep, 3.0V, typical

· Power-Saving Sleep mode

· Wide Operating Voltage Range – 2.0V to 5.5V

· Industrial and Extended Temperature Range

· Low-Power Power-on Reset (POR)

· Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

· Brown-out Detect (BOD)

· Watchdog Timer (WDT) with Independent Oscillator for Reliable Operation

· Multiplexed MCLR/Input Pin

· Interrupt-on-Pin Change

· Individual Programmable Weak Pull-ups

· Programmable Code Protection

· High Endurance Flash/EEPROM Cell

– 100,000 write Flash endurance

– 1,000,000 write EEPROM endurance

– Flash/Data EEPROM Retention: > 40 years

Low-Power Features:

· Standby Current:

– 1 nA @ 2.0V, typical

· Operating Current:

– 8.5 mA @ 32 kHz, 2.0V, typical

– 100 mA @ 1 MHz, 2.0V, typical

· Watchdog Timer Current

– 300 nA @ 2.0V, typical

· Timer1 Oscillator Current:

– 4 mA @ 32 kHz, 2.0V, typical

Peripheral Features:

· 6 I/O Pins with Individual Direction Control

· High Current Sink/Source for Direct LED Drive

· Analog Comparator module with:

– One analog comparator

– Programmable on-chip comparator voltage reference (CVREF) module

– Programmable input multiplexing from device inputs

– Comparator output is externally accessible

· Analog-to-Digital Converter module (PIC12F675):

– 10-bit resolution

– Programmable 4-channel input

– Voltage reference input

· Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler

· Enhanced Timer1:

– 16-bit timer/counter with prescaler

– External Gate Input mode

– Option to use OSC1 and OSC2 in LP mode as Timer1 oscillator, if INTOSC mode selected

· In-Circuit Serial ProgrammingTM (ICSPTM) via two pins

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Peripheral Features:

this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC  Reference Manual” (DS70157).

High-Performance, Modified RISC CPU:

· Modified Harvard architecture

· C compiler optimized instruction set architecture with flexible addressing modes

· 83 base instructions

· 24-bit wide instructions, 16-bit wide data path

· 48 Kbytes on-chip Flash program space (16K instruction words)

· 2 Kbytes of on-chip data RAM

· 1 Kbyte of nonvolatile data EEPROM

· Up to 30 MIPS operation:

– DC to 40 MHz external clock input

– 4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x)

· 30 interrupt sources:

– Three external interrupt sources

– Eight user-selectable priority levels for each

 

· High-current sink/source I/O pins: 25 mA/25 mA

· Timer module with programmable prescaler:

– Five 16-bit timers/counters; optionally pair 16-bit timers into 32-bit timer modules

· 16-bit Capture input functions

· 16-bit Compare/PWM output functions

· 3-wire SPI modules (supports 4 Frame modes)

· I2C™ module supports Multi-Master/Slave mode and 7-bit/10-bit addressing

· Two UART modules with FIFO Buffers

· CAN module, 2.0B compliant

Motor Control PWM Module Features:

· Six PWM output channels:

– Complementary or Independent Output modes

– Edge and Center-Aligned modes

· Three duty cycle generators

· Dedicated time base

· Programmable output polarity

· Dead-time control for Complementary mode

· Manual output control

· Trigger for A/D conversions

Quadrature Encoder Interface Module Features:

 

interrupt source

– Four processor trap sources

· 16 x 16-bit working register array

 

Phase A, Phase B and Index Pulse input 16-bit up/down position counter

Count direction status

Position Measurement (x2 and x4) mode

Programmable digital noise filters on inputs

 

Dual data fetch

Accumulator write-back for DSP operations

Alternate 16-bit Timer/Counter mode

Interrupt on position counter rollover/underflow

 

Modulo and Bit-Reversed Addressing modes

Two, 40-bit wide accumulators with optional saturation logic

Analog Features:

· 17-bit x 17-bit single-cycle hardware fractional/integer multiplier

· All DSP instructions are single cycle

· ±16-bit, single-cycle shift

· 10-bit Analog-to-Digital Converter (ADC) with four Sample and Holde (S&H) inputs:

– 1 Msps conversion rate

– Nine input channels

– Conversion available during Sleep and Idle

· Programmable Brown-out Reset only

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Features

Core: ARM 32-bit Cortex™-M3 CPU

– 36 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory

– Single-cycle multiplication and hardware division Up to 5 timers

– Up to two16-bit timers, each with up to 4 Memories

– 16 to 32 Kbytes of Flash memory

– 4 to 6 Kbytes of SRAM Clock, reset and supply management IC/OC/PWM or pulse counter

– 2 watchdog timers (Independent and Window)

– SysTick timer: 24-bit downcounter

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR and programmable voltage detector (PVD)

– 4-to-16 MHz crystal oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC

– PLL for CPU clock

– 32 kHz oscillator for RTC with calibration Up to 4 communication interfaces

– 1 x I2C interface (SMBus/PMBus)

– Up to 2 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)

– 1 × SPI (18 Mbit/s) CRC calculation unit, 96-bit unique ID

 

Device summary

 

– Sleep, Stop and Standby modes

– VBAT supply for RTC and backup registers

 

Reference

 

Part number

STM32F101C4, Debug mode

– Serial wire debug (SWD) and JTAG interfaces DMA

STM32F101x4

STM32F101x6

STM32F101R4,

STM32F101T4

STM32F101C6,

STM32F101R6,

STM32F101T6

 

– 7-channel DMA controller

– Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs 1 × 12-bit, 1 µs A/D converter (up to 16 channels)

– Conversion range: 0 to 3.6 V

– Temperature sensor Up to 51 fast I/O ports

– 26/37/51 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant

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Analog Peripherals

High Speed 8051 µC Core 10-Bit ADC (C8051F340/1/2/3/4/5/6/7/A/B only)

Pipelined instruction architecture; executes 70% of Up to 200 ksps

Built-in analog multiplexer with single-ended and differential mode

VREF from external pin, internal reference, or VDD

Instructions in 1 or 2 system clocks 48 MIPS and 25 MIPS versions available.

Expanded interrupt handler

·   Built-in temperature sensor

·   External conversion start input option

Two comparators Internal voltage reference

 

Memory

– 4352 or 2304 Bytes RAM

– 64 or 32 kB Flash; In-system programmable in 512-byte

 

(C8051F340/1/2/3/4/5/6/7/A/B only)

– Brown-out detector and POR Circuitry

USB Function Controller

– USB specification 2.0 compliant

– Full speed (12 Mbps) or low speed (1.5 Mbps) operation sectors

Digital Peripherals

– 40/25 Port I/O; All 5 V tolerant with high sink current

– Hardware enhanced SPI™, SMBus™, and one or two enhanced UART serial ports

 

Integrated clock recovery; no external crystal required for full speed or low speed

Supports eight flexible endpoints 1 kB USB buffer memory

Four general purpose 16-bit counter/timers

16-bit programmable counter array (PCA) with five capture/compare modules

External Memory Interface (EMIF)

Integrated transceiver; no external resistors required

 

Clock Sources

On-Chip Debug

Internal Oscillator: ±0.25% accuracy with clock recovery

On-chip debug circuitry facilitates full speed, non-intruenabled. Supports all USB and UART modes sive in-system debug (No emulator required) Provides breakpoints, single stepping, inspect/modify memory and registers

External Oscillator: Crystal, RC, C, or clock (1 or 2 Pin modes)

Low Frequency (80 kHz) Internal Oscillator Superior performance to emulation systems using ICE-chips, target pods, and sockets

Voltage Supply Input: 2.7 to 5.25 V

– Voltages from 3.6 to 5.25 V supported using On-Chip Voltage Regulator

– Can switch between clock sources on-the-fly

Packages

– 48-pin TQFP (C8051F340/1/4/5/8/C)

– 32-pin LQFP (C8051F342/3/6/7/9/A/B/D)

– 5×5 mm 32-pin QFN (C8051F342/3/6/7/9/A/B)

Temperature Range: –40 to +85 °C

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Features

ARM 32-bit Cortex™-M3 CPU Core

– 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access

– Single-cycle multiplication and hardware division

Memories

– 16 or 32 Kbytes of Flash memory

VFQFPN48 (7 × 7 mm)

VFQFPN36 (6 × 6 mm)

– 6 or 10 Kbytes of SRAM Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR, and programmable voltage detector (PVD)

– 4-to-16 MHz crystal oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC

– PLL for CPU clock

– 32 kHz oscillator for RTC with calibration Low power

– Sleep, Stop and Standby modes

– VBAT supply for RTC and backup registers 2 x 12-bit, 1 µs A/D converters (up to 16 channels)

– Conversion range: 0 to 3.6 V

– Dual-sample and hold capability

– Temperature sensor DMA

– 7-channel DMA controller Debug mode

– Serial wire debug (SWD) & JTAG interfaces 6 timers

– Two 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input

– 16-bit, motor control PWM timer with dead-time generation and emergency stop

– 2 watchdog timers (Independent and Window)

– SysTick timer 24-bit downcounter 6 communication interfaces

– 21 x I2C interface (SMBus/PMBus)

– 2 × USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)

– 1 × SPI (18 Mbit/s)

– CAN interface (2.0B Active)

– USB 2.0 full-speed interface

CRC calculation unit, 96-bit unique ID Packages are ECOPACK®

– Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs Up to 51 fast I/O ports

– 26/37/51 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant