Copy Microcontroller PIC16C770 Eeprom
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This document contains device-specific information. Additional information may be found in the PICmicroTM Mid-Range Reference Manual, (DS33023), which may be obtained from your local Micromicrocontroller Sales Representative or downloaded from the Micromicrocontroller website.
The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended copying for a better understanding of the device architecture and operation of the peripheral modules.
There are two memory blocks in each of these PICmicro ® microcontrollers. Each block (Program Memory and Data Memory) has its own bus, so that concurrent access can occur. Additional information on device memory may be found in the PICmicro Mid-Range Reference Manual, (DS33023).
The PIC16C717/770/771 devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. The PIC16C717 and the PIC16C770 have 2K x 14 words of program memory. The PIC16C771 has 4K x 14 words of program memory. Accessing a location above the physically implemented address will cause a wraparound which can facilitate the MCU Cracking.
The reset vector is at 0000h and the interrupt vector is at 0004h. Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain special function registers if Copy Microcontroller. Some frequently used special function registers from one bank are mirrored in another bank for code reduction and quicker access.
The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM.
The special function registers can be classified into two sets; core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in that peripheral feature section.