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Interconnect technology is expanding to include printed systems. As detailed in the iNEMI Organic and Printed Electronics Roadmap,  there is a bounty of printed electronics technologies, such as “drop on demand,” Xerography, micropen, et al. It is not within the scope of this chapter to detail the principles, advantages, benefits, etc., of each technology; rather, it’s important for electronic packaging and interconnect designers to understand the salient features of printed electronics and digital fabrication technologies as well as the similarities and differences among conventional printed circuit technologies and processes.

Digital fabrication can be viewed as the creation of electro-optical-mechanical-thermal systems by means of either parallel or sequential additive processes, as controlled by a digital device. As with any technology, the designer should consider and take advantage of the technology’s features before applying it. In the case of digital fabrication, those features include adaptive, additive, roll-to-roll processes and the ability to fabricate on curved, conformal, curvilinear surfaces.

Most often, digital fabrication is accomplished in a roll-to-roll process, but panel-based digital fabrication is also possible. The revolutionary aspect of digital fabrication, as compared to conventional printed circuit board, is the ability to simultaneously create electronic and/or optical devices, electrical interconnects, mechanical structures, and thermal management systems. For example, using conventional technology and processes, a television remote control is produced by packaging and assembling tens to hundreds of electronic devices onto PCBs and subsequently assembling the PCBs, interconnect, LED, touchpad, etc., within a plastic housing. Digital fabrication would allow the entire system to be fabricated, layer-by-layer, in a fashion similar to that of stereolithography apparatus (SLA). Applying digital fabrication requires a transformation in thinking by electronic system designers: digital fabrication provides for the 2D and 3D design and fabrication of systems that are not limited to electrical interconnect and passive devices.

In digital fabrication, materials with the necessary electrical, mechanical, thermal, and optical properties to form the desired devices, systems, etc., are deposited onto a substrate. Polymer and plastic are the most common substrate materials, due to their compatibility with low-cost, high-through-put processing. However, rigid substrates can be used as well. The materials used in forming electronic devices and interconnect are, typically, conductive inks and dielectrics. Any material, however, that can be dispensed by the dispensing system (“print head” plus material control) can be used. The materials used in forming mechanical and thermal structures, likewise, are defined by the application and limited by the capabilities of the “print head” and material control system. To date, biological, organic, optical, and many types of functional materials have been printed.

Given that devices and structures are being “built-up,” layer-by-layer, there are key differences in the resulting device and feature attributes. For example, vias can be formed as filled or partially filled and can be conductive and/or nonconductive, electrically and/or thermally. Unlike conventional pcb circuit board technology and processes, digital fabrication can be used to produce vias of any geometry. Similarly, individual traces can be of any geometry and can be produced to effect sidewalls with attributes to support application needs. Conductors produced using conventional pcb manufacture technology have sidewalls that are tapered or orthogonal. Digital fabrication could be used to produce conductors with irregular sidewall features, as related to specific performance or mechanical applications. Furthermore, in digital fabrication, mechanical, thermal, and other features could be included in the construction of conductors.

To achieve an optimal interconnect and packaging design, it is important to utilize flexible printed circuit board only when flexible printed circuit board best satisfies application and other needs.

Flexible printed circuit board is a good choice when the primary need is for flexible, conformal, thin, lightweight, etc. Flex is also a good choice for applications requiring comparatively high I/O density, low cost, or performance advantages that cannot be achieved in PCB constructions.  Flexible printed circuit board can be utilized in many applications other than the aforementioned “good choices”; however, the user is strongly encouraged to consider cables, PCB, and other suitable interconnect technologies or else risk unnecessary design complexity, reliability risk, system connector challenges, higher cost, etc. As in conventional electrical design, interconnect must be partitioned according to product specifications including performance, reliability, cost, et al.

Interconnect partitioning, intentional or otherwise, can be found in the hierarchy of interconnects that is in almost any electronic system. For example, although personal computers include state-of-the-art semiconductors and their corresponding nanometer feature sizes, the power for those semiconductors is supplied through cables that are constructed using 18-gauge or larger conductors. Likewise, packaging designers need to partition the interconnect chain to satisfy system specifications, requirements, etc., using “just enough technology.”

The Flexible printed circuit board that interconnects the detector panel and signal processing electronics is a 2ML, 150-micron pitch design. One end of the Flexible printed circuit board is bonded to the panel; the other end is bonded, using ACF, to a multilayer PCB. Multiple ASICs (in bare die form) are attached, in a linear array, on the PCB; the ASICs are wirebonded to the PCB. The ASICs amplify and convert the analog signals produced by the detector panel and route those signals through a connector to a second flexible printed circuit board that connects to the system electronics. The second flexible printed circuit board, because of multiplexing of the digitized signals, requires fewer signal conductors; thus, it is a low-density 2ML flexible printed circuit board (signal plus shield layer).

The next logical step in packaging optimization for this type of electronic system would be the integration of the ASICs and ancillary electronics into the flexible printed circuit board. This integration step, if done properly, would replace the PCB with flexible printed circuit board, reduce the number of interconnects, and reduce detector panel manufacturing steps, without increasing the cost of the flex-PCB-flex system, as above.

The primary challenge in today’s flexible printed circuit board technology is its I/O capability, as determined by minimum feature sizes. For example, in single-metal-layer (1ML) flexible printed circuit, trace and space widths as small as 10-microns have been produced using commercial processes, materials, etc. Even finer features have been produced, a transfer lithography process comprised of 4-micron-pitch (one-micron trace, three-micron space), flexible circuit board configuration. Similarly, feature sizes in two-metal-layer (2ML) flexible circuit board, the lion’s share of commercial flexible circuit board production, have been reduced to twenty-five microns. But minimum trace and space geometries do not tell the entire story of I/O capability for flexible circuit board.

Accordingly, second-level assembly continues to move closer and closer to the device. As witnessed in chip-sized and chip-scale packages, by adapting an existing technology to a novel configuration, the unmet needs for very fine pitch, high volumetric I/O packages effected the reduction in use or elimination of standard electronic packages. Plastic encapsulated lead frames and multilayer ceramic packages have been replaced by plastic encapsulated flex interconnected bare die or, in many cases, by bare die. Similarly, the increasing use of direct chip attach results, in part, from the inability of flex interconnect to meet the constant demand for higher pixel counts in displays. In this case, package interconnect by means of wirebonds with millimeters of length and flex interconnect of tens to hundreds of millimeters in length has been replaced by stud bumps (of tens of microns in diameter, produced using the same wirebonding equipment and materials) and the complete elimination of the flex interconnect. Electronic packaging technologists and applications engineers are currently developing similar system-based solutions and applications by revisions, enhancements, etc., to existing interconnect technologies in order to meet the never-ending demand for greater interconnect density and capability. However, even though its features continue to lag behind those of semiconductors, flexible circuit board has and always will play a significant role in the optimization of system design.

The demand for thin, lightweight, high-density interconnect continues unabated. Similarly, application strategies for satisfying the ever-changing and ever-growing demand for high-density interconnect continue to change. Since their inception, flexible PCB have evolved into a cornerstone technology of high-density interconnect. Flexible PCB has become a fundamental interconnect technology, from its first application in tape automated bonding (TAB) and corresponding simple, point-to-point configurations to the fine-pitch, multilayer designs that are commonplace in today’s mobile electronic products. However, the approaches in using flexible PCB to satisfy the demands of high-performance, highly reliable systems with high volumetric density I/O are still evolving.

Following a familiar path of technology development, the use of flexible PCB has changed from first-level to second-level interconnect applications; More recently, the role of flexible PCB has been expanded to include system-level interconnect. At each point in its changing role in applications, flexible PCB technology has been modified to meet the application demands. For example, to meet the demands of die-to-die interconnect, the single-layer, via-less, point-to-point circuits found in 1970s TAB packaging sprouted additional layers. The transformation to multilayer interconnect required the development of new features such as vias for interconnecting layers; new materials such as adhesives to bond dielectric and conductor layers; and new processes and equipment for manufacturing the resulting incarnation of flexible PCB. As device I/O increased beyond the capabilities of existing multilayer technology, the trace and space features of flexible PCB were reduced. Over the past twenty years, feature sizes in flexible PCB such as conductor geometry, via diameter, dielectric thickness, etc., have been improved significantly. These improvements positioned flexible PCB for its now-dominant position in portable consumer, display, and medical electronics interconnect applications.

As witnessed over the past ten years, the reduction in interconnect feature size has slowed. At the same time, device I/O counts have increased as semiconductor features have decreased, according to Moore’s Law. This disparity in interconnect and semiconductor feature size has created an interconnect “brick wall” that demonstrates the need for advancing the capabilities of interconnect systems. Semiconductor device minimum feature size (and rate of decrease in feature size) far exceeds the equivalent in flexible PCB and PCB Clone technologies. The corresponding gap in interconnect capability has and will limit advances in semiconductor applications until advances in volumetric I/O density, form factor, weight, flexibility, etc., are implemented in flexible PCB. In the meantime, flexible PCB must be utilized as an integral part of the interconnect system.

Although the complexity of electronic systems has increased over the past ten years, the challenges in interconnect systems have been minimized due to the functional partitioning of electronic systems into key subsystems:  encoding/decoding ic, processing, display, and power.

Typically, flexible PCB is utilized for interconnection within a subsystem as well as for system interconnect.

Automated resistivity monitor with threshold

Multiple circuit load (4–up)

Pogo-pin quick connection

Variable-speed motor

Fine-pitch pattern (25mm traces)

Automated data logger

GE Research has also developed a number of TEG monitor cells that are assembled as blocks in a library for use on multiple platforms (RF, DC, analog, PWB, thin core, silicon, etc). The TEG blocks can be assembled in the field area of the panel to aid in process monitoring, second-level assembly, and reliability screening. GE Research has also developed specific tooling to aid in the characterization of thin-core flexible interconnect materials.

Examples of the tools include elongation test stands, flexural endurance systems, and automated electrical testing platforms. The TEG monitors are regularly used in healthcare, military, and commercial flex circuit Manufacturing. These monitors are often used as screening tools for vendor capability demonstrations. Electrical performance, and the corresponding electrical functional testing, is also a critical aspect in flexible printed circuits. Procedures for functional testing are application–specific, but generally, basic function including impedance characterization is tested. Often, users overlook characterization of surface isolation resistance because its adverse impact on electrical performance in low-signal amplitude (microvolts, microamps) applications is not considered or because of the difficulties in obtaining valid data at low-signal amplitudes, especially in the environments required for isolation resistance testing.

The use of flexible printed circuits has become prevalent in diagnostic imaging systems; in particular, the flex shown in Figure 4 is utilized in an ultrasound probe. The circuit shown has features of 4Mm-thick copper, 25Mm-thick polyimide, conductor pitch of 50Mm, and 25Mm-diameter laser-drilled vias.

Test Element Groups (TEGs) or process monitor coupons are critical components in the fabrication of reliable, high-quality flexible interconnect. TEGs are routinely used for standard process control (SPC), certification of compliance (COC), and reliability or qualification testing. A number of standards can be used for interconnect compliance, such as IPC, JDEC, ASTM, etc. TEGs can be utilized as in-process monitors, for post-fabrication validation, and as reliability screening coupons.

In-process monitoring examples include resistivity or Kelvin test structures to insure metal thickness after plating operations. Four-point probe resistivity measurements can be performed, prior to pattern and etch operations, to measure uniformity of metal deposits. Other in-process coupon examples include lithographic resolution structures (critical dimension measurement vehicles), impedance coupons, elongation/ductility coupons, flexural endurance coupons, and via interconnect strings. Via string coupons allow the manufacturer to test an array of vias (200-500) on the device panel for a measure of via integrity during and after flex circuit manufacturing. Via integrity can be measured by passing current through the via structure to insure that sidewall metal coverage is adequate for the circuit operation environment. The via string can combine all metal layers and metal layer pairs to aid in troubleshooting process fabrication issues (via drilling, via cleaning, via metallization). This coupon allows for circuit troubleshooting and, if performed in-process, can save process time and costs by identifying issues early in a process cycle. Specific via string designs allow for accurate measurements of metal contact resistance.

The ability to produce large-area, fine-pitch flexible interconnect is driven by a number of elements. Those elements are comprised of materials, processes, facilities, equipment, design, and engineering support. The demand for thin, fine-pitch flexible interconnect requires unique considerations that are not possible with traditional printed circuit board (PCB) technologies. Fine feature requirements, over large areas, must have clean process facilities and tooling. Most PCB facilities have limited clean-room capabilities and are often restricted to Class 10,000 in the pattern transfer area. Fine-pitch interconnect processing of structures with less than 100um pitch requires clean process areas—i.e., Class 100-1,000–to be able to produce interconnect with acceptable yield. The clean-room facilities must also be augmented with tooling, processes, and operator controls for low-defect densities.

Defects found on flexible interconnect can include trapped fibers, hole in trace, and conductor-to-conductor shorts. These defects are the result of particles generated from process materials or the process environment, including tooling, operators, and the process facility. Many PCB manufacturers have designed clean process tools that contain the work and protect it from an unclean facility.

Flexible printed circuits, with respect to features and process environments, are at the intersection of their semiconductor and printed circuit board equivalents. Fine-pitch flexible interconnect resides at the intersection; tooling, facilities, and expertise from the semiconductor industry are more closely coupled to fine pitch.

The manufacturing process of DOUBLE LAYER PCB BOARD

1 Plot negative film ( photo-plot the negative drawing );

2 Cutting the copper clad laminate ( keep20mmbreak-tab )

3 Drilling hole ( LAMINATE thickness is2.0mm, from drilling bit point to LAMINATE is 1.0-1.5mm, from the smallest drill hole to the biggest drill hole diameter in sequence );

4 Brush and Polish the DOUBLE LAYER PCB BOARD surface to swap off the smear, blurs, furs left after drilling and other residue;

5 Plate copper ( 30mins, the current is around4.5A/m2 );

6 Print photo-sensible circuit pattern ink onto the surface of DOUBLE LAYER PCB BOARD and then cure, film exposure and developing;

7 Plate tin ( around 20-30mins, the current is around 1.5-2.0A/dm2 on the effective area, try the min current first and then fetch it out to check after 3-5mins, if the layer is thin means the current is smaller than expectation, if the surface reflection is white which means the current level is appropriate );

8 After water rinsing these DOUBLE LAYER PCB BOARD and get strip off the film covered on the it, comes to one of the most important steps is ETCHING, strip off the TIN after ETCHING;

9 Print photo-sensitive solder resist ink on the DOUBLE LAYER PCB BOARD by 90T silkscreen frame, the aspect ratio of photo-sensitive ink to curing solution is 3:1, if the ink is too dense to print on the DOUBLE SIDED PCB BOARD, then need to add more diluent to low down is density; Cure the ink after being printed onto the DOUBLE SIDED PCB BOARD, exposure and developing;

10 Print photo-sensitive legend ink by 120T silkscreen frame, the aspect ratio of photo-sensitive ink to curing solution is 3:1, if the ink is too dense to print on the DOUBLE LAYER PCB BOARD, then need to add more diluent to low down is density; Cure the ink after being printed onto the DOUBLE LAYER PCB BOARD;

Test speed is an important factor to choose the right test device. Nail-bed test device can test thousands of point in one time, and flying probe can only test 2 or 4 points in one time. Furthermore, nail-bed test device will consume only 10-150usd for single side, it also depends on the complexity level of PCB. But flying probe will need over 1 hour or even more time to test the same of work. Shipley(1991) has ever explained that even mass production PCB manufacturer will blame flying probe test for its low processing rate, but it is a good choice for low volume and complex PCB manufacturer.

For bare board test, we have dedicated device, one more optimized way for cost is universal device, although this device originally could be more expensive than dedicated device, but it is cost can be offset by installation. Refers to universal grid, PCB with component lead and SMT stand grid is2.5mm. so the test PAD should be greater or equal to1.3mm. for1mmgrid, test PAD should be greater than0.7mm. If grid and probe is so small and fragile that easy to damage. Therefore we had better choose above2.5mmgrid. If universal device and flying probe device can be applied simultaneously, can ensure both commercial and precise measure for high density PCB, another way is conducted rubber test device, this technology can detect those points deviate grid. However, PAD height can vary after HASL which will bring trouble for test point connection.

Normally three different inspection should be committed:

1 bare board test;

2 incircuit test;

3 functional test;

1 Traditional Plated Through Hole;

Most common, cheapest inter-layer connected technology is traditional plated through hole technology. Below picture you can view the 6 layer plated through hole printed circuit board:

In this application, all the drill hole need to be through printed circuit board, no matter if they can be used as via or component lead hole. The drawback of this technology is the through hole will take over all the precious space of each layer. Without the consideration whether that layer need electric connection.

2 Buried via:

Buried via is a kind of through hole technology use to connect the 2 or more layers of multilayer printed circuit board, buried via is among the inner layer of printed circuit board, not on the surface of printed circuit board. See below picture, there is a multilayer printed circuit board with buried via.

Compare with traditional plated through hole structure, buried via can save more space. When the signal circuit density is very high, need more holes to connect the signal layers, and need more signal circuit simultaneously, buried via technology can be applied. However, because buried via technology need more process, so higher circuit density will increase printed circuit board cost.

3 Blind via

Blind via is a kind of through hole which help to connect layer from surface to inner layer, they won’t go through the whole printed circuit board, see below picture

It is a typical blind via technology, blind via technology can be applied on both side of multilayer printed circuit board, blind via can connect both through hole and component hole which will go through printed circuit board.

Blind via can overlay each other and can make smaller which can save more space and layout more signal circuit.

Refers to SMD and connector, blind via is extremely useful because they don’t need big component hole, only need small via which can connect surface layer to inner layer. On the very density and thick multilayer printed circuit board, through surface mount technology can effectively reduce the weight and provide more space for designer.