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Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized.
Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following this table for additional information.
Note 1: Higher capacitance increases the stability of oscillator, but also increases the start- up time.
2: When operating below 3V VDD, or when using certain ceramic resonators at any voltage, it may be necessary to use the HS mode or switch to a crystal oscillator when recover mcu pic18f252 embedded binary.
3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.
4. RS may be required to avoid overdriving crystals with low drive level specification.
5: Always verify oscillator performance over the VDD and temperature range that is expected for the application.
A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency crystal oscillator circuit, or to clock the device up to its highest rated frequency from a crystal oscillator to copy microcontroller pic18f252 flash memory. This may be useful for customers who are concerned with EMI due to high-frequency crystals.
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The HSPLL mode makes use of the HS mode oscillator for frequencies up to 10 MHz. A PLL then multiplies the oscillator output frequency by 4 to produce an internal clock frequency up to 40 MHz. The PLL is enabled only when the oscillator Configura- tion bits are programmed for HSPLL mode. If programmed for any other mode, the PLL is not enabled.