Break IC PIC12F609 Heximal
Break IC PIC12F609 Heximal from eeprom and flash memory, and then transfer the heximal into other blank PIC12F609 which will provide the same functions:
Program Memory Organization
The PIC12F609 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h-03FFh) for the PIC12F609/615/12HV609/615 is physically implemented. Accessing a location above these boundaries will cause a wraparound within the first 1K x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h.
Data Memory Organization
The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank.
Register locations 40h-7Fh in Bank 0 are General Purpose Registers, implemented as static RAM. Register locations F0h-FFh in Bank 1 point to addresses 70h-7Fh in Bank 0. All other RAM is unimplemented and returns ‘0’ when read. The RP0 bit of the STATUS register is the bank select bit.
Break IC PIC12F609 Heximal
The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device. These registers are static RAM.
The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
The STATUS register, shown in Register 2-1, contains:
· the arithmetic status of the ALU
· the Reset status
· the bank select bits for data memory (RAM)
The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended for the purpose of CLONE IC.