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Using the internal oscillator as the clock source elimi- nates the need for up to two external oscillator pins, which can then be used for digital I/O. Two distinct oscillator configurations, which are determined by the FOSCx Configuration bits, are available:

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• In INTIO1 mode, the OSC2 pin (RA6) outputs FOSC/4, while OSC1 functions as RA7 for digital input and output.

In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6. Both are available as digital input and output ports.

The 4x Phase Lock Loop (PLL) can be used with the HF-INTOSC to produce faster device clock speeds than are normally possible with the internal oscillator sources to ensure the success . When enabled, the PLL produces a clock speed of 16 MHz or 64 MHz.

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PLL operation is controlled through software. The control bits, PLLEN (OSCTUNE<6>) and PLLCFG (CONFIG1H<4>), are used to enable or disable its operation. The PLL is available only to HF-INTOSC. The other oscillator is set with HS and EC modes. Additionally, the PLL will only function when the selected output frequency is either 4 MHz or 16 MHz (OSCCON<6:4> = 111, 110 or 101) when duplicating pic18f26k20 source code.

Like the INTIO modes, there are two distinct INTPLL modes available:

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• In INTPLL1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 for digital input and output. Externally, this is identical in appearance to INTIO1.

In INTPLL2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output. Externally, this is identical to INTIO2.

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