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External Memory devices have different timing requirements. To meet these requirements, the XMEM interface provides four different wait-states as shown in Table 5. It is important to consider the timing specification of the External Memory device before selecting the wait-state.

The most important parameters are the access time for the external memory compared to the set-up requirement. The access time for the External Memory is defined to be the time from receiving the chip select/address until the data of this address actually is driven on the bus if Break microcontroller s3f9454 software.

The access time cannot exceed the time from the ALE pulse must be asserted low until data is stable during a read sequence (See tLLRL+ tRLRH – tDVRH in Tables 169 through Tables 176 on pages 376 – 378).

The different wait-states are set up in software. As an additional feature, it is possible to divide the external memory space in two sectors with individual wait-state settings.

This makes it possible to connect two different memory devices with different timing requirements to the same XMEM interface. For XMEM interface timing details, please refer to Table 169 to Table 176 and Figure 161 to Figure 164 in the “External Data Memory Timing” on page 376 after read mcu pic16f688 software.

Note that the XMEM interface is asynchronous and that the waveforms in the following figures are related to the internal system clock. The skew between the internal and external clock (XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Consequently, the XMEM interface is not suited for synchronous operation.

Bit 7 – SRE: External SRAM/XMEM Enable

Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8, ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective data direction registers. Writing SRE to zero, disables the External Memory Interface and the normal pin and data direction set-tings are used.

Bit 6..4 – SRL2:0: Wait-state Sector Limit

It is possible to configure different wait-states for different External Memory addresses. The external memory address space can be divided in two sectors that have separate wait-state bits. The SRL2, SRL1, and SRL0 bits select the split of the sectors, see Table 4 and Figure 14.

By default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory address space is treated as one sector. When the entire SRAM address space is configured as one sector, the wait-states are configured by the SRW11 and SRW10 bits.

Bit 7– XMBK: External Memory Bus-keeper Enable

Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface has tri-stated the lines. Writing XMBK to zero disables the bus keeper. XMBK is not qualified with SRE, so even if the XMEM interface is disabled, the bus keepers are still activated as long as XMBK is one.

Bit 6..3 – Res: Reserved Bits

These bits are reserved and will always read as zero. When writing to this address location, write these bits to zero for compatibility with future devices.

Bit 2..0 – XMM2, XMM1, XMM0: External Memory High Mask

When the External Memory is enabled, all Port C pins are default used for the high address byte. If the full 60KB address space is not required to access the External Memory, some, or all, Port C pins can be released for normal Port Pin function as described in Table 6. As described in “Using all 64KB Locations of External Memory” on page 36, it is possible to use the XMMn bits to access all 64KB locations of the External Memory.

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